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general description the MAX1813 step-down controller is intended for core cpu dc-dc converters in notebook computers. the controller features a dynamically adjustable output (5- bit dac), ultra-fast transient response, high dc accura- cy, and high efficiency necessary for leading-edge cpu core power supplies. maxim? proprietary quick- pwm quick-response, constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on?response to load transients while maintaining a relatively constant switch- ing frequency. the MAX1813 is designed specifically for cpu core applications requiring a voltage-positioned supply. the voltage-positioning input (vpcs), combined with a high-dc-accuracy control loop, is used to implement a power supply that modifies its output set point in response to the load current. this arrangement decreases full-load power dissipation and reduces the required number of output capacitors. the output voltage can be dynamically adjusted through the 5-bit digital-to-analog converter (dac) inputs over a 0.600v to 2v range. the MAX1813 includes an internal multiplexer that selects between three different dac code settings. the first two inputs are controlled by five digital input pins (d0?4). the third input is used for the suspend mode and controlled by two 4-level input pins (s0, s1). output voltage transi- tions are accomplished with a proprietary precision slew-rate control that minimizes surge currents to and from the battery while guaranteeing ?ust-in-time?arrival at the new dac setting. the MAX1813? 28v input range enables single-stage buck conversion from high-voltage batteries for the maximum possible efficiency. alternatively, the con- troller? high-frequency capability combined with two- stage conversion (stepping down the +5v system supply instead of the battery) allows the smallest possi- ble physical size. the MAX1813 is available in a 28-pin qsop package. applications notebook computers (intel imvp ii /coppermine ) docking stations cpu core supply single-stage (batt to v core ) converters two-stage (+5v to v core ) converters features high-efficiency voltage positioning quick-pwm architecture 1% v out accuracy over line adjustable output slew rate 0.600v to 2v adjustable output range (5-bit dac) 2v to 28v battery input range 200/300/600/1000khz switching frequency output undervoltage and overvoltage protection drives large synchronous-rectifier mosfets 20% accurate current-limit 10a shutdown supply current 2v 1% reference output power-good (pgood) indicator small 28-pin qsop package MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ________________________________________________________________ maxim integrated products 1 ordering information 19-2010; rev 0; 4/01 for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp. range pin-package MAX1813eei -40 c to +85 c 28 qsop quick-pwm is a trademark of maxim integrated products, inc. coppermine and imvp- ? are trademarks of intel corp. typical operating circuit appears at end of data sheet. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dh lx bst d0 d1 d2 pgnd d3 d4 code zmode sus v dd dl gnd pgood ilim ref ton v cc s1 s0 cc fb time skp/sdn vpcs v+ qsop top view MAX1813 pin configuration
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: skp/ sdn may be forced to 12v, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto- type breadboards, using the no-fault test mode. v+ to gnd ..............................................................-0.3v to +30v v cc , v dd to gnd .....................................................-0.3v to +6v pgnd to gnd.....................................................................0.3v d0 d4, code, zmode, sus, pgood to gnd ......-0.3v to +6v skp/ sdn to gnd (note 1) .....................................-0.3v to +16v ilim, fb, cc, ref, ton, time, s0, s1 to gnd......................-0.3v to (v cc + 0.3v) vpcs to gnd ............................................................-2v to +30v dl to pgnd................................................-0.3v to (v dd + 0.3v) bst to pgnd..........................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) lx to bst..................................................................-6v to +0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70 c) 28-pin qsop (derate 10.8mw/ c above +70 c)..........860mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.925v to 2.0v -1 +1 v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.700v to 0.900v -1.5 +1.5 dc output voltage accuracy (notes 2, 3) v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.600v to 0.675v -1.83 +1.83 % vpcs input bias current i vps v vpcs = 0 or 28v -1 +1 a vpcs transconductance g m v vpcs = 0 to -100mv 18 20 22 s vpcs linear input range 100 mv fb input resistance r fb 115 180 265 k ? 38khz nominal, r time = 470k ? -12 +12 150khz nominal, r time = 120k ? -8 +8 time frequency accuracy 380khz nominal, r time = 47k ? -12 +12 % ilim input leakage current i ilim v ilim = 0 or 5.0v 0.01 100 na v+ = 5.0v, v fb = 1.2v ton = gnd 250 270 290 ton = ref 165 190 215 ton = open 320 355 390 on-time (note 4) t on v+ = 12v, v fb = 1.2v ton = v cc 465 515 563 ns ton = ref, open, or v cc 400 500 minimum off-time (note 4) t off ( min ) ton = gnd 300 375 ns bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 1.4 2.5 ma
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point <1 5 a quiescent supply current (v+) i+ measured at v+ 25 40 a shutdown supply current (v cc ) skp/ sdn = gnd 2 5 a shutdown supply current (v dd ) skp/ sdn = gnd <1 5 a shutdown supply current (v+) skp/ sdn = gnd, v cc = v dd = 0 or 5v <1 5 a reference voltage v ref v cc = 4.5v to 5.5v, -40 a i ref +40 a 1.98 2 2.02 v ref fault lockout voltage falling edge, 1% hysteresis 1.5 1.6 1.7 v fault protection code = gnd 2.20 2.25 2.30 output overvoltage fault preset threshold v ovp measured at fb code = v cc 1.95 2.00 2.05 v output overvoltage fault propagation delay t ovp fb forced to 2% above trip threshold 1.5 s output undervoltage fault threshold with respect to unloaded output voltage 60 70 80 % output undervoltage fault propagation delay fb forced to 2% below trip threshold 10 s output undervoltage fault- blanking time from skp/ sdn signal going high, clock speed set by r time 256 clks current-limit threshold (positive, default) v ith v gnd - v vpcs , ilim = v cc 40 50 60 mv v ilim = 0.5v 40 50 60 current-limit threshold (positive, adjustable) v ith v gnd - v vpcs v ilim = 2v (ref) 143 200 265 mv negative current-limit threshold v gnd - v vpcs , with respect to v ith , ilim = v cc -72 -56 -40 mv zero-crossing current-limit threshold v gnd - v vpcs 5mv thermal shutdown threshold rising temperature, hysteresis = 15 c 160 c v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, switching disabled below this level 4.05 4.45 v pgood lower trip threshold measured at fb with respect to unloaded output voltage, falling edge -15 -12.5 -10.5 % pgood upper trip threshold measured at fb with respect to unloaded output voltage, rising edge 81012% pgood propagation delay falling edge, fb forced 2% below or above pgood trip threshold 1.5 s pgood output low voltage i sink = 1ma 0.4 v pgood leakage current high state, forced to 5.5v 1 a
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units gate drivers dh gate driver on-resistance r on ( d h ) v bst - v lx forced to 5v 1.2 3.5 ? high state (pull up) 1.3 3.5 dl gate driver on-resistance r on ( dl ) low state (pull down) 0.4 1.0 ? dh gate driver source/sink current i dh dh forced to 2.5v, v bst - v lx forced to 5v 2.0 a dl gate driver sink current i dl dl forced to 5v 4.0 a dl gate driver source current i dl dl forced to 2.5v 1.3 a dl rising 35 dead time dh rising 26 ns logic and i/o logic input high voltage v ih d0 ? d4, code, sus, zmode; v cc = 4.5v to 5.5v 2.4 v logic input low voltage v il d0 ? d4, code, sus, zmode; v cc = 4.5v to 5.5v 0.8 v dac z-mode programming resistor, low d0 ? d4, 0 to 0.4v or 2.6v to 5.5v applied to the resistor, zmode = code = gnd or zmode = code = v cc 1.05 k ? dac z-mode programming resistor, high d0 ? d4, 0 to 0.4v or 2.6v to 5.5v applied to the resistor, zmode = code = gnd or zmode = code = v cc 95 k ? pull up 40 d0 ? d4, code pull up/down entering impedance mode pull down 8 k ? d0 ? d4, code = v cc -1 +1 logic input current sus, zmode = gnd or v cc -1 +1 a 4-level logic input high (v cc ) ton (200khz operation), s0, s1 v cc - 0.4 v 4-level logic input upper- middle (float) ton (300khz operation), s0, s1 2.8 3.85 v 4-level logic input lower- middle (ref) ton (600khz operation), s0, s1 1.65 2.35 v 4-level logic low (gnd) ton (1000khz operation), s0, s1 0.5 v skp/ sdn high input level (skip mode) 2.8 6.0 v skp/ sdn float input level (forced-pwm mode) 1.4 2.2 v skp/ sdn low input level (shutdown mode) 0.5 v
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) electrical characteristics (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = -40 c to +85 c , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units skp/ sdn no fault input level 12 15 v skp/ sdn , 4-level logic input current skp/ sdn , ton, s0, s1 = gnd or v cc -3 3 a parameter symbol conditions min max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.925v to 2.0v -1 +1 v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.700v to 0.900v -1.5 +1.5 dc output voltage accuracy (notes 2, 3) v+ = 4.5v to 28v, vpcs = gnd, dac codes from 0.600v to 0.675v -1.83 +1.83 % vpcs input bias current i vps v vpcs = 0 or 28v -1 +1 a v vps = 0 to -40mv 18 22 vpcs transconductance g m v vps = 0 to -100mv 16.5 22 s fb input resistance r fb 115 265 k ? 380khz nominal, r time = 47k ? -12 +12 150khz nominal, r time = 120k ? -8 +8 time frequency accuracy 38khz nominal, r time = 470k ? -12 +12 % ilim input leakage current i ilim v ilim = 0 or 5.0v 100 na v+ = 5.0v, v fb = 1.2v ton = gnd 250 290 ton = ref 165 215 ton = open 320 390 on-time (note 4) t on v+ = 12v, v fb = 1.2v ton = v cc 465 563 ns ton = ref, open, or v cc 500 minimum off-time (note 4) t off ( m in ) ton = gnd 375 ns bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 2.5 ma quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point 5 a quiescent supply current (v+) i+ measured at v+ 40 a shutdown supply current (v cc ) skp/ sdn = gnd 5 a shutdown supply current (v dd ) skp/ sdn = gnd 5 a
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = -40 c to +85 c , unless otherwise noted.) (note 5) parameter symbol conditions min max units shutdown supply current (v+) skp/ sdn = gnd, v cc = v dd = 0 or 5v 5 a reference voltage v ref v cc = 4.5v to 5.5v, -40 a i ref +40 a 1.98 2.02 v ref fault lockout voltage falling edge, 1% hysteresis 1.5 1.7 v fault protection code = gnd 2.20 2.30 output overvoltage fault preset threshold v ovp measured at fb code = v cc 1.95 2.05 v output undervoltage fault threshhold with respect to unloaded output voltage 60 80 % current-limit threshold (positive, default) v ith v gnd - v vpcs , ilim = v cc 40 60 mv v ilim = 0.5v 40 60 current-limit threshold (positive, adjustable) v ith v gnd - v vpcs v ilim = 2v (ref) 143 265 mv negative current-limit threshold v gnd - v vpcs , with respect to v ith , ilim = v cc -75 -35 mv v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, switching disabled below this level 4.05 4.45 v pgood lower trip threshold measured at fb with respect to unloaded output voltage, falling edge -15 -10.5 % pgood upper trip threshold measured at fb with respect to unloaded output voltage, rising edge 812% pgood output low voltage i sink = 1ma 0.4 v pgood leakage current high state, forced to 5.5v 1 a gate drivers dh gate driver on-resistance r on ( d h ) v bst - v lx forced to 5v 3.5 ? high state (pull up) 3.5 dl gate driver on-resistance r on ( dl ) low state (pull down) 1.0 ? logic and i/o logic input high voltage v ih d0 ? d4, code, sus, zmode; v cc = 4.5v to 5.5v 2.4 v logic input low voltage v il d0 ? d4, code, sus, zmode; v cc = 4.5v to 5.5v 0.8 v dac z-mode programming resistor, low d0 ? d4, 0 to 0.4v or 2.6v to 5.5v applied to the resistor, zmode = code = gnd or zmode = code = v cc 1.05 k ? dac z-mode programming resistor, high d0 ? d4, 0 to 0.4v or 2.6v to 5.5v applied to the resistor, zmode = code = gnd or zmode = code = v cc 95 k ? d0 ? d4, code = v cc -1 +1 logic input current sus, zmode = gnd or v cc -1 +1 a
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning _______________________________________________________________________________________ 7 note 2: output voltage accuracy specifications apply to dac voltages from 0.6v to 2.0v. note 3: when the inductor is in continuous conduction, the output voltage will have a dc regulation level higher than the error-com- parator threshold by 50% of the ripple. in discontinuous conduction (skp/ sdn = v cc , light load), the output voltage will have a dc regulation level higher than the trip level by approximately 1.5% due to slope compensation. note 4: on-time and off-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times may be differ- ent due to mosfet switching speeds. note 5: specifications to -40 c are guaranteed by design, not production tested. electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, vpcs = zmode = gnd = pgnd, skp/ sdn = code = v cc , v out set to 1.5v, t a = -40 c to +85 c , unless otherwise noted.) (note 5) parameter symbol conditions min max units 4-level logic input high (v cc ) ton (200khz operation), s0, s1 v cc - 0.4 v 4-level logic input upper- middle (float) ton (300khz operation), s0, s1 2.8 3.85 v 4-level logic input lower- middle (ref) ton (600khz operation), s0, s1 1.65 2.35 v 4-level logic low (gnd) ton (1000khz operation), s0, s1 0.5 v skp/ sdn high input level (skip mode) 2.8 6.0 v skp/ sdn float input level (forced-pwm mode) 1.4 2.2 v skp/ sdn low input level (shutdown mode) 0.5 v skp/ sdn no fault input level 12 15 v skp/ sdn , 4-level logic input current skp/ sdn , ton, s0, s1 = gnd or v cc -3 +3 a
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 8 _______________________________________________________________________________________ typical operating characteristics (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.) 100 50 0.01 0.1 1 10 100 efficiency vs. load current (v out = 1.4v) 60 MAX1813 toc01 load current (a) efficiency (%) 70 80 90 a1 b1 c1 d1 c2 d2 b2 a2 100 50 0.01 0.1 1 10 100 efficiency vs. load current (v out = 1.1v) 60 MAX1813 toc02 load current (a) efficiency (%) 70 80 90 a1 b1 c1 d1 c2 d2 b2 a2 100 50 0.01 0.1 1 10 100 effective efficiency vs. load current (v out = 1.4v) 60 MAX1813 toc03 load current (a) effective efficiency (%) 70 80 90 a1 b1 c1 d1 c2 d2 b2 a2 100 50 0.01 0.1 1 10 100 effective efficiency vs. load current (v out = 1.1v) 60 MAX1813 toc04 load current (a) effective efficiency (%) 70 80 90 a1 b1 c1 d1 c2 d2 b2 a2 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 010 5 15202530 output voltage vs. load current (v out = 1.4v) MAX1813 toc05 load current (a) output voltage (v) v batt = 24v v batt = 7v pwm mode skip mode 010 5 15202530 output voltage vs. load current (v out = 1.1v) MAX1813 toc06 load current (a) output voltage (v) 1.00 1.04 1.02 1.08 1.06 1.12 1.10 1.14 v batt = 24v v batt = 7v pwm mode skip mode 0 50 100 150 200 250 300 350 400 010 5 15202530 switching frequency vs. load current MAX1813 toc07 load current (a) switching frequency (khz) pwm mode skip mode v out = 1.4v v batt = 7v 275 285 295 305 315 325 08 4 12162024 switching frequency vs. battery input voltage MAX1813 toc08 battery input voltage (v) switching frequency (khz) i out = 10a v out = 1.4v v out = 1.1v efficiency curve legend skip mode (skip = gnd) a1: v+ = 4.5v b1: v+ = 7v c1: v+ = 15v d1: v+ = 24v pwm mode (skip = v cc ) a2: v+ = 4.5v b2: v+ = 7v c2: v+ = 15v d2: v+ = 24v
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning _______________________________________________________________________________________ 9 220 260 240 300 280 320 340 -40 10 -15 35 60 85 switching frequency vs. temperature MAX1813 toc09 temperature ( c) switching frequency (khz) i out = 20a i out = 10a i out = 5a i out = 1a 260 280 300 320 340 360 380 400 420 -40 -15 10 35 60 85 on time vs. temperature MAX1813 toc10 temperature ( c) on time (ns) i out = 1a i out = 5a i out = 20a i out = 10a -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85 current-limit deviation vs. temperature MAX1813 toc11 temperature ( c) v vpcs deviation (mv) v ilim = 0.5v v ilim = 2v 0 0.4 0.2 0.8 0.6 1.0 1.2 0812 4 162024 no-load supply current vs. battery input voltage (skip mode) MAX1813 toc12 battery input voltage (v) supply current (ma) i cc + i dd v out = 1.4v skp/sdn = v cc code = zmode = gnd i batt 0 5 10 15 20 25 30 35 40 08 4 12162024 no-load supply current vs. battery input voltage (pwm mode) MAX1813 toc13 battery input voltage (v) supply current (ma) i cc + i dd i batt v out = 1.4v skp/sdn = float code = zmode = gnd 1000 10 10 100 1000 transition frequency vs. r time MAX1813 toc14 r time (k ? ) f slew (khz) 100 t a = -40 c, 25 c, 85 c typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 10 ______________________________________________________________________________________ 40 s/div output overload waveform 40a 0 a b MAX1813 toc18 0 -100mv 20a 100mv a. i out = 0 to 40a, (0 to 35m ? ), 20a/div b. v out = 1.4v, 1v/div c. vpcs, 200mv/div ilim = v cc 1.4v c 40 s/div dynamic transition (zmode transition) 5v 0 a b MAX1813 toc19 -10a 1.2v 5v 1.3v a. v zmode = 0 to 5v, 5v/div b. pgood, 5v/div c. inductor current, 10a/div d. v out = 1.3v to 1.15v, i out = 1a, 100mv/div code = v cc 10a 0 1.1v c d 40 s/div dynamic transition (sus transition) 5v 0 a b MAX1813 toc20 -5a 1.3v 5v -15a a. v sus = 0 to 5v, 5v/div b. pgood, 5v/div c. inductor current, 10a/div d. v out = 1.3v to 0.85v, i out = 1a, 500mv/div code = v cc 15a 5a 0.85v c d typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.) 20 s/div load transient (pwm mode) 20a 0 a b MAX1813 toc15 1.41v 1.31v 10a 1.36v a. i out = 0.3a to 22a, 10a/div b. v out = 1.4v, 50mv/div skp/sdn = float 20 s/div load transient (skip mode) 20a 0 a b MAX1813 toc16 1.41v 1.31v 10a 1.36v a. i out = 0.3a to 22a, 10a/div b. v out = 1.4v, 50mv/div skp/sdn = v cc 20 s/div load transient (voltage positioning disabled) 20a 0 a b MAX1813 toc17 1.46v 1.36v 10a 1.41v a. i out = 0.3a to 22a, 10a/div b. v out = 1.4v, 50mv/div skp/sdn = float
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 11 200 s/div startup waveform (heavy load) 1.6v 0 a b MAX1813 toc21 0 0 5v 20a a. v skp/sdn = 0 to 1.6v, 2v/div b. pgood, 5v/div c. v out = 1.4v, r out = 63m ? , 1v/div d. inductor current, 20a/div 0 1.4v c d 200 s/div startup waveform (no load, pwm mode) 1.6v 0 a b MAX1813 toc22 0 0 5v 10a a. v skp/sdn = 0 to 1.6v, 2v/div b. pgood, 5v/div c. v out = 1.4v, no load, 1v/div d. inductor current, 10a/div 0 1.4v c d 200 s/div startup waveform (no load, skip mode) 5v 0 a b MAX1813 toc23 0 0 5v 10a a. v skp/sdn = 0 to 5v b. pgood, 5v/div c. v out = 1.4v, no load, 1v/div d. inductor current, 10a/div 0 1.4v c d 40 s/div shutdown waveform 1.6v 0 a b MAX1813 toc24 1.4v 0 20a a. v skp/sdn = 0 to 1.6v, 2v/div b. pgood, 5v/div c. v out = 1.4v, r out = 63m ? , 1v/div d. inductor current, 20a/div 0 c d 5v typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 12 ______________________________________________________________________________________ pin description pin name function 1v+ battery voltage sense connection. connect v+ to the input power source. v+ is used only for pwm one-shot timing. dh on-time is inversely proportional to the input voltage over a 2v to 28v range. 2 vpcs current-sense input. connect a current-sense resistor (r sense ) between vpcs and pgnd. the voltage on vpcs controls both the voltage-positioning and current-limit circuits. the slope of the voltage-positioned output is controlled with the current-sense resistor and the gain resistor connected between cc and ref. see setting voltage positioning . the current-limit threshold is set by ilim. if the current-sense signal (inductor current r sense ) exceeds the current-limit threshold, the MAX1813 will not initiate a new cycle. vpcs can also be connected to lx to reduce component count, but cc must be connected to ref to disable the voltage positioning. 3 skp/ sdn combined shutdown and skip-mode control. drive skp/ sdn to gnd for shutdown, leave skp/ sdn open for low-noise forced-pwm mode, or drive to v cc for normal pulse-skipping operation: shutdown mode: skp/ sdn = gnd low-noise forced-pwm mode: skp/ sdn = open normal pulse-skipping operation: skp/ sdn = v cc low-noise forced pwm mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. forcing skp/ sdn with 12v to 15v clears the fault latch and disables undervoltage protection, overvoltage protection, and thermal shutdown with otherwise normal pulse- skipping operation. exiting shutdown clears the fault latch. do not connect skp/ sdn to voltages over 15v. 4 time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew-rate clock. a 470k ? to 47k ? resistor sets the clock from 38khz to 380khz, respectively: f slew = 150khz x 120k ? / r time . 5 fb feed b ack inp ut. c onnect fb to the j uncti on of the exter nal i nd uctor and outp ut cap aci tor ( fi g ur e 1) . 6cc compensation capacitor and voltage-positioning gain adjustment. connect a 47pf to 1000pf (47pf typ) capacitor from cc to gnd to adjust the loop s response time. connect a resistor (r avps ) from cc to ref to set the gain of the voltage positioning amplifier. where the voltage-positioning amplifer s transconductance (g m ) is typically 20 s. 7, 8 s0, s1 suspend-mode voltage select inputs. s0 and s1 are 4-level logic inputs that select the suspend- mode vid code for for the suspend-mode multiplexer inputs. if sus is high, the suspend-mode vid code is delivered to the dac. see suspend-mode internal mux . 9v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) through a series 20 ? resistor. bypass to gnd with a 0.22 f or greater capacitor as close to the MAX1813 as possible. 10 ton on-time selection-control input. this is a 4-level input used to determine dh on-time. connect to gnd, ref, or v cc , or leave ton unconnected to set the following switching frequencies: gnd = 1000khz, ref = 600khz, floating = 300khz, and v cc = 200khz. vv gr v v out out prog m avps vpcs ref =+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 13 pin description (continued) pin name function 11 ref +2.0v reference voltage output. bypass to gnd with a 0.22 f or greater capacitor. the reference can sink and source 40 a (min) for external loads. loading ref degrades fb accuracy according to the ref load regulation error. 12 ilim current-limit adjustment. the pgnd - vpcs current-limit threshold defaults to 50mv if ilim is tied to v cc . in adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ilim over a 500mv to 2.0v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. connect ilim to ref for a fixed 200mv threshold. 13 pgood open-drain power-good output. pgood is normally high when the output is in regulation. if v fb is not within a +10%/-12.5% window of the dac setting, pgood is asserted low. during dac code transitions, pgood is forced high until 1 clock period after the slew-rate controller finishes the transition. pgood is low in shutdown, undervoltage lockout, and during soft-start. any fault condition forces pgood low, and it remains low until the fault is cleared. 14 gnd analog ground 15 pgnd power ground. pgnd is one of the inputs to the current-limit comparator. 16 dl low-side gate-driver output. dl swings from gnd to v dd . dl is forced high when a fault occurs, and at the end of the shutdown sequence. 17 v dd supply input for the dl gate drive. connect to the system supply voltage (4.5v to 5.5v). bypass to pgnd with a 1 f or greater capacitor. 18 sus suspend-mode control input. when sus is high, the suspend-mode vid code, as programmed by s0 and s1, is delivered to the dac. sus overrides zmode. connect sus to gnd if the suspend-mode multiplexer is not used. see table 6. 19 zmode performance-mode mux contol input. if sus is low, zmode selects between two different vid codes. if zmode = gnd with code = v cc , or zmode = v cc with code = gnd, the vid code is set by the logic-level voltages on d0 ? d4. when initially entering impedance mode, the vid code is determined by the impedance at d0 ? d4. see tables 5 and 7. 20 code code select input. code acts like another vid code input to select between the intel mobile voltage position ii (imvp-ii ) or coppermine vid codes. code also determines the polarity of the zmode input. see tables 5 and 7. 21 ? 25 d4 ? d0 vid code inputs. d0 is the lsb and d4 is the msb of the internal 5-bit dac (see tables 5 and 7). if zmode = gnd with code = v cc , or zmode = v cc with code = gnd, d0 ? d4 are high-impedance digital inputs, and the vid code is set by the logic-level voltages on d0 ? d4. when initially entering impedance mode, the vid code is determined by the impedance at d0 ? d4 as follows: logic low = source impedance is 1k ? 5% logic high = source impedance is 100k ? 5%. 26 bst boost flying-capacitor connection. connect to an external capacitor and diode according to the standard high-power application circuit (figure 1). an optional resistor in series with bst allows dh pullup current to be adjusted. 27 lx external inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. lx does not connect to the current-limit comparator. 28 dh high-side gate driver output. dh swings from lx to bst.
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 14 ______________________________________________________________________________________ detailed description the MAX1813 buck controller is targeted for low-volt- age, high-current cpu core power supplies for note- book computers, which typically exhibit 0 to 22a (or greater) load steps. the proprietary quick-pwm pulse- width modulator in the converter is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency cur- rent-mode pwms while also avoiding the problems caused by widely varying switching frequencies in con- ventional constant on-time and constant off-time pfm schemes. +5v bias supply (v cc and v dd ) the MAX1813 requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebook s 95% efficient +5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v supply can be generated with an external linear regulator. the +5v bias supply powers v cc (pwm controller) and v dd (gate-drive power). the maximum current is: i bias = i cc + sw (q g1 + q g2 ) = 15ma to 45ma (typ) where i cc is 1.4ma (typ), sw is the switching frequen- cy, and q g1 and q g2 are the mosfet total gate- charge specification limits at v gs = 5v. the battery input (v+) and +5v bias inputs (v cc and v dd ) can be connected together if the input source is a fixed 4.5v to 5.5v supply. if the +5v bias supply is powered up prior to the battery supply, the enable sig- nal (skp/ sdn ) must be delayed until the battery volt- age is present in order to ensure startup. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a constant-on- time, current-mode type with voltage feed-forward v cc c out d2 l1 0.68 h 1.4v output up to 22a pgood ilim d1 c2 1 f c bst 0.1 f q h q l c1 1 f r1 20 ? c in battery (v batt ) 7v to 24v cc time +5v input bias supply power-good indicator dl lx v+ dh bst vpcs pgnd gnd zmode fb ton v dd MAX1813 ref sus s1 s0 d0 code d2 d1 d3 d4 to v cc open suspend mode open r gate 100k ? r time 120k ? r avps 150k ? c ref 0.22 f c comp 47pf open (forced-pwm) open (300khz) r sense r vpcs 100 ? r fb 100 ? c vpcs 1nf c fb 1nf skp/sdn note: see table 1 for complete list of component values figure 1. standard high-power application circuit
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 15 (figure 2). this architecture relies on the output ripple voltage to provide the pwm ramp signal. thus, the out- put filter capacitor s equivalent series resistance (esr) acts as a feedback resistor. the control algorithm is simple: the high-side switch on-time is determined sole- ly by a one-shot whose period is inversely proportional to input voltage and directly proportional to output volt- age (see on-time one-shot ). another one-shot sets a minimum off-time (400ns typ). the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the input and output voltages. the high- side switch on-time is inversely proportional to v+ and directly proportional to the output voltage as set by the dac code. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequen- cy clock generator. the benefits of a constant switch- ing frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in component circuit 1 (figure 1) output voltage 0.6v to 1.75v input voltage range 7v to 24v maximum load current 22a inductor 0.68 h sumida cdep134h-0r6 or panasonic etqp6f0r6bfa frequency 300khz (ton = float) high-side mosfet international rectifier (2) irf7811a low-side mosfet fairchild (3) fds7764a or international rectifier (3) irf7822a input capacitor (6) 10 f, 25v taiyo yuden tmk432bj106 or tdk c4532x5r1e106m output capacitor (6) 220 f panasonic eefue0e221r current-sense resistor 1.5m ? dale wsl 2512, plus 0.5m ? copper pc board trace ilim level v cc (default) voltage-positioning gain resistor 150k ? m a nuf act urer ph one [ c oun try co de] website mosfets fairchild semiconductor [1] 888- 522-5372 www.fairchildsemi.com international rectifier [1] 310- 322-3331 www.irf.com siliconix [1] 203- 268-6261 www.vishay.com capacitors kemet [1] 408- 986-0424 www.kemet.com panasonic [1] 847- 468-5624 www.panasonic.com sanyo [ 65] 281- 3226 ( s i ng ap or e) [ 1] 408- 749- 9714 www.secc.co.jp taiyo yuden [03] 3667- 3408 (japan) [1] 408- 573-4150 www.t-yuden.com inductors coilcraft [1] 800- 322-2645 www.coilcraft.com coiltronics [1] 561- 752-5000 www.coiltronics.com sumida [1] 408- 982-9660 www.sumida.com table 1. component selection for standard applications table 2. component suppliers
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 16 ______________________________________________________________________________________ toff one-shot ton gnd v cc ref cc pgood vpcs chip supply from dac trig q s set clr r q q ton one-shot 2v ref ref +10% 5-bit r-2r dac ref -12% trig q s set clr r q q lx vpcs dh bst v batt 5v to 24v 5v bias supply ilim v+ ref pgnd dl v dd d0 code zmode d1 d2 d3 d4 sus fb s0 s1 time soft-start zero crossing 2v ref skp/sdn ton compute ovp/uvp detect osc decoder (see figure 6) and slew-rate controller MAX1813 5v bias gm 9r r v out figure 2. functional diagram
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 17 easy design methodology and predictable output volt- age ripple. where k is set by the ton pin-strap connection, and 75mv is an approximation to accommodate for the expected drop across the low-side mosfet switch and current-sense resistor (table 3). the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics table. on-times at operating points far removed from the conditions specified can vary over a wide range. for example, the 1000khz setting will typically run about 10% slower with inputs much greater than +5v, due to the very short on-times required. although the on-time is set by ton, the input voltage, and the output voltage, other factors also contribute to the overall switching frequency. the on-time guaran- teed in the electrical characteristics table is influenced by switching delays in the external high-side mosfet. resistive losses including the inductor, both mosfets, output capacitor esr, and pc board copper losses in the output and ground tend to raise the switching frequency at higher output currents. switch dead-time can increase the effective on-time, reducing the switching frequency. this effect occurs only in pwm mode (skp/ sdn = float) when the inductor cur- rent reverses at light or negative load currents. with reversed inductor current, the inductor s emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead-time (26ns typ). when the controller operates in continuous mode, the dead-time is no longer a factor, and the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, includ- ing high-side switch, inductor, and pc board resis- tances; and t on is the on-time calculated by the MAX1813. automatic pulse-skipping switchover in skip mode (skp/ sdn = high, table 4), an inherent automatic switchover to pfm takes place at light loads (figure 3). this switchover is controlled by a comparator that truncates the low-side switch on-time at the inductor current s zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. for a 7v to 24v input volt- age range, this threshold is relatively constant, with ?= + +? sw out drop1 on in drop1 drop2 (v v ) t(v v v ) t k(v 75mv) v on out in = + ton setting (khz) k-factor ( s) approximate k-factor error (%) minimum recommended v batt at v out = 1.4v (v) 200 4.9 9 1.8 300 3.3 10 2.0 600 1.8 13 2.9 1000 1.05 13 3.5 table 3. approximate k-factor errors inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 3. pulse-skipping/discontinuous crossover point
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 18 ______________________________________________________________________________________ only a minor dependence on the input voltage: where k is the on-time scale factor (table 3). the load- current level at which pfm/pwm crossover occurs (i load(skip) ) is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 3). for example, in the standard application circuit with k = 3.3s (300khz), v in = 12v, v out = 1.4v, and l = 0.68h, switchover to pulse-skipping operation occurs at i load = 3.0a or about 1/4 full load. the crossover point occurs at an even lower value if a swinging (soft- saturation) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the induc- tor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input voltage levels). forced-pwm mode the low-noise, forced-pwm mode (skp/ sdn left float- ing, table 4) disables the zero-crossing comparator that controls the low-side switch on-time. the resulting low-side gate-drive waveform is forced to be the com- plement of the high-side gate-drive waveform. this, in turn, causes the inductor current to reverse at light loads because the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency nearly constant, but it results in higher no-load supply current that can be 15ma to 45ma, depending on the external mosfets and switching frequency. the MAX1813 uses forced-pwm mode during all transi- tions, while the slew-rate controller is active. during downward output voltage transitions, forced-pwm allows the MAX1813 to sink current, thereby rapidly pulling down the output voltage. when a transition uses high negative inductor current, due to voltage position- ing, the output voltage may not settle to its intended final value until after the slew-rate controller terminates. for this reason, most applications should use pwm mode exclusively, although skip mode is beneficial in the low-power suspend state (see shutdown and mode control ). shutdown and mode control (skp/ sdn ) when skp/ sdn is driven low, the MAX1813 enters the low-current shutdown mode (table 4). shutdown forces pgood low immediately and ramps down the output voltage in 25mv increments at the clock rate set by r time . once the output voltage ramps down, the MAX1813 pulls dh low, forces dl high, and shuts down the reference, so the total supply current (i cc + i dd + i+) drops to 4a (typ). when skp/ sdn is left floating or driven high, the MAX1813 begins the startup sequence. first, the refer- ence powers up. after the reference exceeds its 1.6v undervoltage lockout threshold, the dac determines the target output voltage and starts ramping up the out- put voltage. the slew-rate controller increases the out- ik v 2l vv v load(skip) out in out in ? ? ? ? ? ? ? ? ? ? ? ? ? skp/ sdn dl mode comments gnd high shutdown micropower shutdown state (i cc = 2 a typ). v cc switching normal operation automatic switchover from pwm mode to pulse-skipping pfm mode at light loads. prevents inductor current from recirculating into the input. float switching forced pwm low-noise forced-pwm mode causes inductor current to reverse at light loads and suppresses pulse-skipping operation. 12v switching no-fault test mode test mode with overvoltage, undervoltage, and thermal shutdown faults disabled. otherwise, the converter operates as if skp/ sdn = v cc . v cc or float high fault the fault latch set by the overvoltage protection, output undervoltage protection, or thermal shutdown. the MAX1813 will remain in fault mode until v cc power is cycled or skp/ sdn is forced low. table 4. operating mode truth table
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 19 put voltage in 25mv increments at the clock rate set by r time until the MAX1813 reaches the selected output voltage. the MAX1813 does not feature traditional vari- able current-limit soft-start, so full output current is immediately available. once the slew-rate controller ter- minates, output undervoltage fault blanking period ends, and the output voltage is in regulation, pgood goes high. leave skp/ sdn floating for forced-pwm operation, or connect skp/ sdn to v cc for normal operation. during all transitions, the MAX1813 uses pwm mode while the slew-rate controller is active. exiting shutdown clears the fault latch. current-limit circuit (ilim) the current-limit circuit employs a unique valley cur- rent-sensing algorithm. if the current-sense signal is above the current-limit threshold, the MAX1813 will not initiate a new cycle (figure 4). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore the exact current-limit characteristic and maximum load capabili- ty are a function of the current-limit threshold, inductor value, and input voltage. the reward for this uncertainty is robust, loss-less over-current sensing. when com- bined with the undervoltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sink- ing current. the negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ilim is adjusted. the MAX1813 measures the current by sensing the voltage between vpcs and pgnd. connect an external sense resistor between the source of the low-side n- channel mosfet and pgnd. the signal provided by this current-sense resistor is also used for voltage posi- tioning (see setting voltage positioning ). reducing the sense voltage increases the relative measurement error. however, the configuration eliminates the uncer- tainty of using the low-side mosfet on-resistance to measure the current, so the resulting current-limit toler- ance is tighter when sensing with a 1% sense resistor. the voltage at ilim sets the current-limit threshold. for voltages from 500mv to 2v, the current-limit threshold voltage is precisely 0.1 x v ilim . set this voltage with a resistive divider between ref and gnd. the current- limit threshold defaults to 50mv when ilim is tied to v cc . the logic threshold for switchover to this 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors don t corrupt the cur- rent-sense signals seen by vpcs and gnd. the ic must be mounted close to the current-sense resistor with short, direct traces making a kelvin sense connec- tion (see pc board layout guidelines ). mosfet gate drivers (dh and dl) the dh and dl drivers are optimized for driving mod- erate-sized, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the MAX1813 will interpret the mosfet gate as off while there is actually charge still left on the gate. use very short, wide traces (50 to 100 mils wide if the mos- fet is 1 inch from the device). the dead time at the other edge (dh turning off) is determined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.4 ? (typ) on-resistance. this helps pre- vent dl from being pulled up during the fast rise-time of the lx node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, for high-current applications, some combinations of high- and low-side fets may cause excessive gate-drain coupling, leading to poor inductor current i limit i load 0 time i peak figure 4. valley current-limit threshold point
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 20 ______________________________________________________________________________________ efficiency, emi, and shoot-through currents. this is often remedied by adding a resistor less than 5 ? in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 5). dac converter (d0-d4) the digital-to-analog converter (dac) programs the output voltage. it receives a preset digital code from the cpu pins, digital logic, general-purpose i/o, or an external multiplexer. do not leave d0 d4 floating; use 1m ? or less pullups if the inputs may float. the state of do d4 can be changed while the switch- mode power supply is active, initiating a transition to a new output voltage level. during this interval, the slew- rate controller is active, so the MAX1813 uses forced- pwm mode. if this mode of dac control is used, connect zmode low. change d0 d4 together, avoid- ing greater than 1s skew between bits. otherwise, incorrect dac readings may cause a partial transition to the wrong voltage level, lengthening the overall tran- sition time. the available dac codes and resulting out- put voltages (table 5) are compatible with the coppermine and intel s mobile voltage positioning ii (imvp-ii ) specifications. vid code options (code) the MAX1813 contains two separate sets of vid codes. the code pin selects between the two output voltage tables (table 5). drive code low to select the older 0.925v to 2.000v dac codes, which are compatible with the coppermine specifications. drive code high to select the new 0.600v to 1.750v dac codes, which are compatible with the imvp-ii specifications. code also determines the polarity of zmode (table 7). suspend-mode operation (s0, s1) when the cpu clock stops, the processor enters sus- pend mode and requires a lower supply voltage to min- imize power consumption. the MAX1813 includes suspend-mode output voltages that are selected using two 4-level input pins (s0 and s1, table 6). when the cpu clock stops, drive sus high to transition to the suspend-mode output voltage. during the transition, the MAX1813 asserts forced-pwm mode to sink current and pull down the output voltage until pgood goes high. when sus is driven high, suspend mode overrides the 5-bit dac setting. when sus is low, the MAX1813 determines the output voltage from the 5-bit dac (d0 d4), code, and zmode settings. internal multiplexers (zmode, sus) the MAX1813 has a unique internal multiplexer that can select one of three different vid code settings for different processor states. depending on the logic level at sus, the suspend (sus) mode multiplexer selects the vid code settings from either the d0-d4 input decoder or the s0/s1 input decoder. the zmode multi- plexer selects one of the two d0-d4 input modes, set- ting the vid code based on either the voltage on d0-d4 (logic mode) or the impedance decoder output (imped- ance mode) (figure 6). when sus is high, the suspend-mode multiplexer selects the vid code from the s0/s1 input decoder. the decoder outputs are determined by inputs s0 and s1 (table 6). when sus is low, the suspend-mode multi- plexer selects the d0-d4 input decoder output. in logic mode (table 7), the logic-level voltages on d0- d4 set the dac settings. in this mode, the inputs are continuously active and can be dynamically changed by external logic. the logic-mode vid code setting is typically used for the battery-mode state, and the source of this code is sometimes the vid pins of the cpu with suitable pullup resistors. impedance mode (table 7) is programmed by external resistors in series with d0 d4, using a unique scheme that allows two sets of data bits using only one set of pins. when the MAX1813 initially enters impedance mode, the resistances at d0 d4 are sampled by the impedance decoder to see if there is a large resistance in series with the pin. if the voltage level on a dac input pin is a logic low, an internal switch connects that pin to bst +5v v batt 5 ? typ dh lx MAX1813 figure 5. reducing the switching-node rise time
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 21 output voltage (v) d4 d3 d2 d1 d0 code = 0 code = 1 0 0 0 0 0 2.000 1.750 0 0 0 0 1 1.950 1.700 0 0 0 1 0 1.900 1.650 0 0 0 1 1 1.850 1.600 0 0 1 0 0 1.800 1.550 0 0 1 0 1 1.750 1.500 0 0 1 1 0 1.700 1.450 0 0 1 1 1 1.650 1.400 0 1 0 0 0 1.600 1.350 0 1 0 0 1 1.550 1.300 0 1 0 1 0 1.500 1.250 0 1 0 1 1 1.450 1.200 0 1 1 0 0 1.400 1.150 0 1 1 0 1 1.350 1.100 0 1 1 1 0 1.300 1.050 0 1 1 1 1 no cpu* 1.000 1 0 0 0 0 1.275 0.975 1 0 0 0 1 1.250 0.950 1 0 0 1 0 1.225 0.925 1 0 0 1 1 1.200 0.900 1 0 1 0 0 1.175 0.875 1 0 1 0 1 1.150 0.850 1 0 1 1 0 1.125 0.825 1 0 1 1 1 1.100 0.800 1 1 0 0 0 1.075 0.775 1 1 0 0 1 1.050 0.750 1 1 0 1 0 1.025 0.725 1 1 0 1 1 1.000 0.700 1 1 1 0 0 0.975 0.675 1 1 1 0 1 0.950 0.650 1 1 1 1 0 0.925 0.625 1 1 1 1 1 no cpu* 0.600 table 5. output voltage vs. dac codes *in the no cpu state, dh and dl are held low and the slew-rate controller is set for 0.425v.
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 22 ______________________________________________________________________________________ an internal 40k ? pullup for about 4s to see if the pin voltage can be forced high (figure 7). if the pin voltage cannot be pulled to a logic high, the pin is considered low impedance, and its impedance-mode logic state is low. if the pin can be pulled to a logic high, the imped- ance is considered high and so is the impedance- mode logic state. similarly, if the voltage level on the pin is a logic high, an internal switch connects the pin to an internal 8k ? pulldown to see if the pin voltage can be forced low. if so, the pin is high impedance, and its impedance-mode logic state is high. in either sampling condition, if the pin s logic level does not change, the pin is determined to be low impedance, and the imped- ance-mode logic state is low. a high pin impedance (logic high) is 100k ? or greater, and a low impedance (logic low) is 1k ? or less. the guaranteed levels for these impedances are 95k ? and 1.05k ? to allow the use of standard 100k ? and 1k ? resis- tors with 5% tolerance. output voltage transition timing (time) the MAX1813 is designed to perform output voltage transitions in a controlled manner, automatically mini- mizing input surge currents. this feature allows the cir- cuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. this makes the ic very suit- able for imvp-ii cpus and other cpus that operate in two or more modes with different core voltage levels. the imvp-ii cpus operate at multiple clock frequencies and require multiple core voltages. when transitioning *float = no connection d0 d1 d2 d3 d4 code zmode zmode mux s0/s1 decoder code sel0 sel1 out out 01 or 10 in impedance decoder in out 00 or 11 sus mux sus out dac 1 0 s0 s1 sus d0-d4 decoder out MAX1813 (figure 7) figure 6. internal multiplexers block diagram s1 s0 output voltage (v) gnd gnd 0.975 gnd ref 0.950 gnd float* 0.925 gnd v cc 0.900 ref gnd 0.875 ref ref 0.850 ref float* 0.825 ref v cc 0.800 float* gnd 0.775 float* ref 0.750 float* float* 0.725 float* v cc 0.700 v cc gnd 0.675 v cc ref 0.650 v cc float* 0.625 v cc v cc 0.600 table 6. suspend-mode output voltages code zmode 0 0 impedance mode 0 1 logic mode 1 0 logic mode 1 1 impedance mode table 7. zmode polarity table
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 23 from one clock frequency to another, the cpu first goes into a low-power state, then the output voltage and clock frequency are changed. the change must be accomplished in 100s or the system may halt. at the beginning of an output voltage transition, the MAX1813 forces the pgood output high. pgood remains masked high until the slew-rate controller has set the internal dac to the final value and one addition- al slew-rate clock period has passed. the output voltage transition is performed in 25mv increments, preceded by a 4s delay and followed by one additional clock period after which pgood will remain high if the output voltage is in regulation. the total time for a transition depends on r time , the voltage difference, and the accuracy of the MAX1813 s slew- rate clock. the greater the output capacitance, the higher the surge current required for the transition. the MAX1813 will automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ilim. the transition time is given by: where slew = 150khz x 120k ? /r time , v old is the original output voltage, and v new is the new output voltage. see time frequency accuracy in electrical characteristics for slew accuracy. the practical range of r time is 47k ? to 470k ? , corre- sponding to 2.6s to 26s per 25mv step. although the dac takes discrete 25mv steps, the output filter makes the transitions relatively smooth. the average inductor current required to make an output voltage transition is: power-on reset and undervoltage lockout v cc undervoltage lockout (uvlo) circuitry inhibits switching, forces pgood low, and forces the dl gate driver high. if the v cc voltage drops below 4.2v, it is assumed that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, dl is forced high in this mode; this will force the output to ground. this results in large nega- tive inductor current and possibly small negative output voltages. if v cc is likely to drop in this fashion, the out- put can be clamped with a schottky diode to pgnd to reduce the negative excursion. power-on reset (por) occurs when v cc rises above approximately 2v. this resets the fault latch and pre- pares the pwm for operation. when v cc rises above 4.2v, the dac inputs are sampled, and the output volt- age begins to slew to the dac setting. to ensure cor- rect startup, v+ should be present before v cc . if the converter attempts to bring the output into regulation without v+ present, the fault latch will trip. for automat- ic startup, the battery voltage (v+) should be present before v cc . the skp/ sdn pin can be forced low or v cc power cycled to reset the fault latch. power-good output (pgood) pgood is the open-drain output of a window compara- tor. this power-good output remains high impedance as long as the output voltage is within +10%/-12.5% of the regulation voltage. when the output voltage is greater than 10% or less than the -12.5% window limits, the internal mosfet is activated and pulls the output low. while the slew-rate controller is active (except dur- ing startup and shutdown), the MAX1813 forces pgood high. pgood is low in shutdown, input under- voltage lockout, and during startup. any fault condition forces pgood low until the fault is cleared. for logic- level output voltages, connect an external pullup resis- tor between pgood and v cc (or v dd ). a 100k ? resistor works well in most applications. i c 25mv l out slew ?? t 4s + 1 1+ v-v 25mv tran slew old new ? ? ? ? ? ? ? ? ? ? ? ? ? ? 26k ? d4 d3 d2 d1 d0 26k ? 26k ? 26k ? 26k ? 8k ? 100k ? 8k ? 8k ? 8k ? 8k ? 3.0v to 5.5v 100k ? +5v b-data latch v cc gnd MAX1813 figure 7. internal mux impedance-mode data test and latch
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 24 ______________________________________________________________________________________ output overvoltage protection the overvoltage protection circuit is designed to pro- tect the cpu against a shorted high-side mosfet by drawing high current and activating the battery s pro- tection circuit. the output voltage is continuously moni- tored for overvoltage. if the output exceeds the overvoltage threshold, the fault protection is triggered and the circuit shuts down. the dl low-side gate-driver output latches high, which turns on the synchronous- rectifier mosfet with 100% duty and, in turn, rapidly discharges the output filter capacitor, forcing the output to ground. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery s protection circuit will engage. the MAX1813 is latched off and won t restart until skp/ sdn is toggled or v cc power is cycled. overvoltage protection can be defeated using the no- fault test mode (see no-fault test mode ). output undervoltage protection the output undervoltage protection (uvp) function is similar to foldback current limiting but employs a timer rather than a variable current limit. if the MAX1813 out- put voltage is under 70% of the nominal value, the pwm is latched off and won t restart until skp/ sdn is toggled or v cc power is cycled. to allow startup, uvp is ignored during the undervoltage fault-blanking time (the first 256 cycles of the slew rate after startup). uvp can be defeated using the no-fault test mode (see no-fault test mode ). thermal fault protection the MAX1813 features a thermal fault protection circuit. when the temperature rises above +160 c, the dl low- side gate-driver output latches high until skp/ sdn is toggled or v cc power is cycled. the threshold has +15 c of thermal hysteresis, which prevents the regula- tor from restarting until the die cools off. thermal shutdown can be defeated using the no-fault test mode (see no-fault test mode ). no-fault test mode the over/undervoltage protection features can compli- cate the process of debugging prototype breadboards since there are at most a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to disable the overvoltage protection, under- voltage protection, and thermal shutdown features, and clear the fault latch if it has been set. in no-fault test mode, the regulator operates as if skp/ sdn were high (skip mode). forcing 12v to 15v on skp/ sdn activates no-fault test mode. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) x 80%. switching frequency: this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in2 . the optimum frequen- cy is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. inductor operating point: this choice provides trade- offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size but poor efficiency and high output noise. the min- imum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the MAX1813 s pulse-skipping algorithm initiates skip mode at the critical-conduction point. thus, the induc- tor operating point also determines the load-current value at which pfm/pwm switchover occurs. the opti- mum operating point is usually found between 20% and 50% ripple current. the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil-
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 25 ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time: where t off(min) is the minimum off-time (see electrical characteristics ), and k is from table 3. inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 22a, v in = 12v, v out = 1.4v, f sw = 300khz, 30% ripple current, or lir = 0.3. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ). i peak = i load(max) + (i load(max) x lir / 2) setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: where i limit(low) equals the minimum current-limit threshold voltage divided by r sense . for the 50mv default setting, the minimum current-limit threshold is 40mv. connect ilim to v cc for a default 50mv current-limit threshold. in the adjustable mode, the current-limit threshold is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd, with ilim connected to the center tap. the external 0.5v to 2.0v adjustment range corre- sponds to a 50mv to 200mv current-limit threshold. when adjusting the current limit, use 1% tolerance resistors and a 10a divider current to prevent a signifi- cant increase of errors in the current-limit tolerance. output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition with- out tripping the overvoltage protection circuit. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitor s size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r esr = v step(max) / i load(max) the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag equation in the design procedure ). the amount of over- shoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. output capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the boundary of insta- bility is given by the following equation: v il 2c v soar peak 2 out out i ) >i - i lir 2 limit(low load(max) load(max) ? ? ? ? ? ? l 1.4v (12v -1.4v) 12v 300khz 22a 0.3 0.62 h = = l v(vv) v i lir out in out in sw load(max) = ? ? v l(i -i ) vk v + t 2c v (v - v )k v - t sag load1 load2 2 out in off(min) out out in out in off(min) = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 26 ______________________________________________________________________________________ where: for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in wide-spread use at the time of publication have typical esr zero frequencies below 30khz. in the standard application used for inductor selection, the esr needed to support a 30mvp-p ripple is 30mv/(22a x 0.3) = 4.5m ? . six 220f/2.5v panasonic sp capaci- tors in parallel provide 2.5m ? (max) esr. the capaci- tors typical esr results in a zero at 48khz. don t put high-value ceramic capacitors directly across the output without taking precautions to ensure stability. ceramic capacitors have a high esr zero frequency and may cause erratic, unstable operation. however, it s easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and the fb pin. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feed-back loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there isn t enough volt- age ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immedi- ately after the minimum off-time period has expired. double-pulsing is more annoying than harmful, result- ing in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can cause the out- put voltage to rise above or fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to monitor simultaneously the inductor current with an ac current probe. don t allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the MAX1813 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>20a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. the high-side mosfet (q h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of q h . conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of q h . if v in does not vary over a wide range, the minimum power dissipation occurs where the resis- tive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two so-8s, dpak or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems may occur. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (q h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: i=i v(v-v) v rms load out in out in ? esr esr out = 1 2r c ? ? esr sw =
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 27 generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation specifications often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses don t usually become an issue until the input is greater than approxi- mately 15v. calculating the power dissipation in the high-side mos- fet (q h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pc board layout charac- teristics. the following switching-loss calculation provides only a very rough estimate and is no substi- tute for breadboard evaluation, preferably including verification using a thermocouple mounted on q1: where c rss is the reverse transfer capacitance of q h , and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac-adapter voltages are applied, due to the squared term in the c x v in 2 x sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (q l ), the worst-case power dissipation always occurs at the maximum input voltage: the worst case mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, you can overdesign the circuit to tolerate: where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good size heatsink to handle the overload power dissipation. choose a schottky diode (d1) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/3 of the load current. this diode is optional and can be removed if efficiency isn t critical. setting voltage positioning voltage positioning dynamically changes the output voltage set point in response to the load current. when the output is loaded, the signal fed back from the vpcs input adjusts the output voltage set point, thereby decreasing power dissipation. the load-transient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. to under- stand the benefits of dynamically adjusting the output voltage, see voltage positioning and effective efficiency . the amount of output voltage change is adjusted by an external gain resistor (r avps ). place r avps between ref and cc (figure 8). the voltage developed across the current-sense resistor (v vpcs ) relates to the output voltage as follows: where v out(prog) is the programmed output voltage set by the dac code (table 5), and the vpcs transcon- ductance (g m ) is typically 20s (see electrical characteristics ). the MAX1813 contains internal clamps to limit the voltage positioning between 10% below and 2% above the programmed output voltage. the MAX1813 determines the load current from the voltage across the current-sense resistor (r sense ) between the source of the low-side mosfet and pgnd. therefore, the current-sense voltage present at vpcs is determined by: v=-ir (1-d) vpcs load sense v=v 1+ gr v v out out(prog) m avps vpcs ref ? ? ? ? ? ? ? ? ? ? ? ? ? ? i=i + i lir 2 load limit(high) load(max) ? ? ? ? ? ? ? ? pd q sistive l (re ) = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1- v v ir out in(max) load 2 ds(on) pd q switching h sw () = ? vc i i in(max) 2 rss load gate pd q sistive h (re ) = vi r v out load 2 ds(on) in
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 28 ______________________________________________________________________________________ where d = v out /v in is the regulator s duty cycle. however, since the ratio of the output-to-input voltage is usually relatively large, the effect of the duty cycle on the circuit s performance is not significant. therefore, the complete expression for the voltage-positioned out- put depends upon the load current, the value of the voltage-positioning gain resistor, and the value of the current-sense resistor: the MAX1813 voltage-positioning circuit has several advantages over older circuits, which added a fixed voltage offset on the sense point and used a low-value resistor in series with the output. the new circuit uses the same current-sense resistor for both voltage posi- tioning and current-limit detection. this simultaneously provides accurate current limiting and voltage position- ing. since the new circuit adjusts the output voltage within the control loop, the voltage-positioning signal may be internally amplified. the additional gain allows the use of low-value current-sense resistors, so the power dissipated in this sense resistor is significantly lower than a single resistor connected directly in series with the output. the current-sense signal from the sense resistor to the vpcs pin should be filtered to eliminate the effect of switching noise on the voltage-positioned output. a simple low-pass rc filter with a 100ns time constant (100 ? x 1000pf) sufficiently reduces the noise on the current-sense signal (figure 8). voltage-positioning compensation (cc) the voltage-positioning compensation capacitor filters the amplified vpcs signal, allowing the user to adjust the dynamics of the voltage-positioning loop. since the output impedance of the transconductance amplifier is much greater than r avps , the pole provided by this node can be approximated by 1/(2 r avps c comp ). the response time is set with a 47pf to 1000pf capacitor from cc to gnd. applications information voltage positioning and effective efficiency powering new mobile processors requires careful attention to detail to reduce cost, size, and power dissi- pation. as cpus became more power hungry, it was recognized that even the fastest dc-dc converters were inadequate to handle the transient power require- ments. after a load transient, the output instantly changes by esr cout x ? i load . conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 9). however, the cpu only requires that the out- put voltage remains above a specified minimum value. dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces power consumption under load. for a conventional (nonvoltage-positioned) circuit, the total voltage change is: vv 1- gr r i v out out(prog) m avps sense load ref ? ? ? ? ? ? ? ? ? ? ? ? ? ? MAX1813 q 2 dl vpcs cc ref pgnd gnd r sense r vpcs c vpcs c ref r avps c comp figure 8. voltage-positioning block diagram b 1.4v 1.4v a a. conventional converter (50mv/div) b. voltage-positioned output (50mv/div) voltage positioning the output figure 9. voltage positioning the output
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 29 v p-p1 = 2 x (esr cout x ? i load ) + v sag + v soar where v sag and v soar are defined in figure 10. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases (figure 9). so the total voltage change for a voltage-positioned circuit is: v p-p2 = (esr cout x ? load ) + v sag + v soar where v sag and v soar are defined in the design procedure . since the amplitudes are the same for both circuits (v p-p1 = v p-p2 ), the voltage-positioned circuit requires only twice the esr. since the esr specifica- tion is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit. an additional benefit of voltage positioning is reduced power consumption at high load currents. because the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r sense . however, the gain of the voltage positioning block reduces the power dissipation in r sense . for a nominal 1.4v, 22a output (r load = 63.6m ? ), reducing the output voltage 6% gives a 1.32v output voltage and a 20.7a output current. given these values, cpu power consumption is reduced from 30.8w to 27.3w. the additional power consumption of r sense is: 2.0m ? x (20.7a) 2 = 0.86w and the overall power savings is: 30.8w - (27.3w + 0.86w) = 2.62w in effect, 2.62w of cpu dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. effective efficiency is defined as the efficiency required of a non-voltage- positioned circuit to equal the total dissipation of a volt- age-positioned circuit for a given cpu operating condition. calculate effective efficiency: 1) start with the efficiency data for the positioned circuit v in , i in , v out , i out ). 2) model the load resistance for each data point: r load = v out / i out 3) calculate the output current that would exist for each r load data point in a nonpositioned application: i np = v np / r load where v np = 1.4v (in this example). 4) calculate effective efficiency as: effective efficiency = (v np x i np ) / (v in x i in ) = calcu- lated nonpositioned power output divided by the measured voltage-positioned power input. 5) plot the efficiency data point at the nonpositioned current, i np . the effective efficiency of voltage-positioned circuits is shown in the typical operating characteristics . dropout performance the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher fre- quencies (table 3). also, keep in mind that transient- response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure ). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of ability to slew the inductor current higher in response to increased load and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases unless additional output capacitance is used. i load capacitor soar (energy in l transferred to c out ) capacitive sag (dv/dt = i out /c out ) recovery esr step-down and step-up (i step x esr) v out figure 10. transient-response regions
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 30 ______________________________________________________________________________________ a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see on-time one-shot ), t off(min) is from the electrical charact- eristics table, and k is taken from table 3. the absolute minimum input voltage is calculated with h = 1. if the calculated v+ (min) is greater than the required minimum input voltage, then reduce the operating fre- quency or add output capacitance to obtain an accept- able v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example: v out = 1.4v sw = 600khz k = 1.8s; worst-case k = 1.58s t off(min) = 500ns v drop1 = v drop2 = 100mv calculating again with h = 1 gives the absolute limit of dropout: therefore, v in must be greater than 2.2v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 2.9v. using skip mode during suspend for most active cpu modes, the minimum load cur- rents are too high to benefit from pulse-skipping opera- tion, so pwm mode should be used exclusively. skip mode can, in fact, be a hindrance to properly executing output voltage transitions (see forced pwm mode ). however, processor suspend currents can be low enough to benefit from low-power pulse skipping. for processors with three-state outputs, skp/ sdn and sus may be directly controlled. if only digital logic is available, skp/ sdn and sus may be controlled with two digital outputs with the circuit shown in figure 11. in normal operation, skp/ sdn remains biased at 2v by the resistive voltage-divider and the MAX1813 s internal circuitry. when the circuit goes into suspend mode (sus high), the pin remains biased at 2v for approxi- mately 200s before it goes high. this delay causes the MAX1813 to remain in pwm mode long enough to correctly complete the negative output voltage transi- tion to the suspend-state voltage. thereafter, the MAX1813 will operate with low-quiescent-current skip mode. when the circuit returns to normal operation (sus low), the delay on the skp/ sdn does not affect the transition dynamics because the MAX1813 auto- matically returns to pwm mode and continues to supply current until the output is in regulation. the on/ off signal overrides both normal forced-pwm operation and suspend mode. using the zmode multiplexer there are many ways to use the versatile zmode multi- plexer. the preferred method will depend on when and how the vid dac codes for the various states are determined. if the output voltage codes are fixed at pc board design time, program both codes with a simple combination of pin-strap connections and series resis- tors (figure 12). if the output voltage codes are chosen during pc board assembly, both codes can be inde- pendently programmed with resistors (figure 13). this matrix of 10 resistor-footprints can be programmed to all possible logic-mode and impedance-mode code combinations with only 5 resistors. often, the cpu pins provide one set of codes that are typically used with pullup resistors to provide the logic mode vid code, and resistors in series with d0 d4 set the impedance-mode code. since some of the cpu s vid pins may float, the open-circuit pins can present a problem for the zmode multiplexer s impedance mode. for impedance mode to work, any pins intended to be low during this mode must appear to be low impedance at least for the 4s sampling interval. v in min () . = ? ? ? ? ? ? ? +?= 1.4v+100mv 1- (0.5 s 1.0/1.58 s) 100mv 100mv 2 v 2 v in min () . = ? ? ? ? ? ? ? +?= 1.4v+100mv 1- (0.5 s 1.5/1.58 s) 100mv 100mv 2 v 9 v in min () = v+v 1- ht k vv out drop1 off(min) drop2 drop1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? +?
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 31 MAX1813 d4 d3 d2 d1 d0 zmode 3.0v to 5.5v zmode high vid = 01010 1.25v zmode low vid = 01100 1.15v 100k ? 100k ? zmode = high = 1.25v zmode = low = 1.15v figure 12. using the internal mux with hard-wired logic-mode and impedance-mode dac codes MAX1813 d4 d3 d2 d1 d0 zmode zmode = high = 1.25v zmode = low = 1.15v 1k ? 1k ? 100k ? 1k ? 100k ? 2.7v to 5.5v note: use pullup for logic mode 1, pulldown for logic mode 0. use 100k ? for impedance mode 1, 1k ? for impedance mode 0. figure 13. using the internal mux with both vid codes resistor-programmed figure 11. three-state operating mode control skp/sdn inv1 r1 120k ? sus v cc inv2 inv3 r2 80k ? r3 30k ? c1 10nf on/off suspend suspend skip (2.8v to 6v) MAX1813 operating mode forced-pwm (1.4v to 2.2v) shutdown (0 to 0.5v) t delay t delay MAX1813 on/off
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 32 ______________________________________________________________________________________ if the cpu s vid pins float, the open-circuit pins can present a problem for the MAX1813 s internal mux. the processor s vid pins can be used for the voltage-mode setting, together with suitable pullup resistors. however, the impedance mode vid code is set with resistors in series with d0 d4, and for the impedance mode to work, any pins intended to be impedance mode logic low must appear to be low impedance, at least for the 4s sampling interval. use one of the two following methods to make the d0- d4 inputs appear low impedance (figure 14). by using low-impedance pullup resistors with the cpu s vid pins, each pin provides the low impedance needed for the mux to correctly interpret the impedance-mode set- ting. unfortunately, the low resistances cause several ma of additional quiescent current for each of the cpu s grounded vid pins. since d0 d4 need to briefly appear low impedance for sampling, the additional qui- escent current may be avoided by using high-imped- ance pullups that are bypassed with a large enough capacitance to make them appear low impedance for the 4s sampling interval. as noted in figure 14, 4.7nf capacitors allow the inputs to appear low impedance even though they are pulled up with 1m ? resistors. in some cases, it is desirable to determine the imped- ance-mode code during system boot so that several processor types can be used without hardware modifi- cations. figure 15 shows one way to implement this configuration. the desired code is determined by the system bios and programmed into one register of the max1609 using the smbus serial interface. the max1609 s other register is left in its power-up state (all outputs high impedance). when smbsus is low, the outputs are high impedance and do not affect the logic-mode vid code setting. when smbsus is high, the programmed register is selected, and the max1609 forces a low impedance on the appropriate vid input pins. the zmode signal is delayed relative to the smb- sus pin because the vid pins that are pulled low by the max1609 take significant time to rise when they are released. one additional benefit of using the max1609 for this application is that the application uses only five of the max1609 s high-volt- age, open-drain outputs. the other three outputs can be used for other purposes. adjusting v out with a resistive-divider the output voltage can be adjusted with a resistive- divider rather than the dac if desired (figure 16). the drawback is that the on-time doesn t automatically receive correct compensation for changing output volt- age levels. this can result in variable switching fre- quency as the resistor ratio is changed, and/or exces- sive switching frequency. the equation for adjusting the output voltage is: where v fb is the currently selected dac value, and r int is the fb input resistance. in resistor-adjusted cir- cuits, the dac code should be set as close as possible to the actual output voltage to minimize the shift in switching frequency. offsetting the output voltage when required, accurate positive and negative output voltage adjustments may be made using external resis- tors to offset the feedback voltage. place an offset resistor between the output and fb. the offset voltage may then be controlled by adjusting the current across this offset resistor. for a positive voltage offset, connect a resistor between fb and gnd to sink current as shown in figure 17. for a negative offset voltage, place a resistor between ref and fb to source current as shown in figure 18. the reference can only support 40a of current, so a unity-gain buffer must be used to generate the negative offset reference voltage. select r fb to be between 50 ? and 500 ? to avoid output voltage regulation error from the fb pin s input current. adjusting v out above 2v the feed-forward circuit that makes the on-time depen- dent on the input voltage maintains a nearly constant switching frequency as the input voltage (i load ) and the dac code are changed. this works extremely well as long as fb is connected directly to the output. when the output is adjusted with a resistive-divider, the switching frequency is increased by the inverse of the divider ratio. this change in frequency can be compensated with the addition of a resistive-divider to the battery-sense input (v+). attach a resistor-divider from the battery voltage v= r r_ (v v ) os(neg) fb out(prog) ref ? ? ? ? ? v= r r_ v os(pos) fb out(prog) ? ? ? ? v=v1+ r4 r5 r out fb int ? ? ? ? ? ? smbus is a trademark of intel corp.
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 33 3.3v 100k ? 100k ? 100k ? 100k ? 100k ? 100k ? vid4 vid3 vid2 vid1 vid0 1nf gmuxsel smbus address smbus data clock add0 add1 0 1 0 1 0 1 1 1 1 1 3.3k ? zmode cpu MAX1813 3.3v max1609 100k ? 100k ? 100k ? 100k ? MAX1813 d4 d3 d2 d1 d0 zmode * to reduce quiescent current, 1k ? pullup resistors can be replaced by 1m ? resistors with 4.7nf capacators in parallel. zmode high vid = 01010 1.25v cpu vid = 01100 1.15v (zmode low) 1k ? 1m ? 1k ? 1k ? 1k ? 1k ? 4.7nf *optional 3.15v to 5.5v 100k ? 100k ? cpu zmode = high = 1.25v zmode = low = 1.15v figure 14. using the internal mux with cpu driving the logic-mode cid code figure 15. using the zmode multiplexer
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 34 ______________________________________________________________________________________ figure 16. adjusting v out with a resistive-divider MAX1813 dh lx vpcs pgnd dl gnd fb v out c out q l c fb c vpcs r vpcs q h r4 r5 l1 r sense v out = v fb (1 + r4/r5) MAX1813 dh lx vpcs pgnd dl gnd ref fb v out c out q 2 c fb c vpcs r vpcs q 1 r fb r1 r2 r3 logic add0 add1 control logic inh r4 l1 r sense c ref max4634 figure 17. adding a positive offset voltage
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 35 to v+ on the MAX1813, with the same attenuation factor as the output divider. the v+ input has a nominal 600k ? input impedance, which should be considered when selecting resistor values. one-stage (battery input) vs. two-stage (5v input) applications the MAX1813 can be used with a direct battery con- nection (one stage) or can obtain power from a regulat- ed 5v supply (two stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. the transient response of the single stage is better due to the ability to ramp the inductor current faster. the total efficiency of a single stage is better than the two-stage approach. the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pc board traces. although the two-stage design has slow- er transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. however, they are also expensive and brittle, and their ultra-low esr characteristic can result in excessively high esr zero frequencies. in addition, their relatively low capac- itance value can cause output overshoot when step- ping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored inductor energy. in some cases, there may be no room for electrolytics, creating a need for a dc-dc design that uses nothing but ceramics. the MAX1813 can take advantage of the small size and low esr of ceramic output capacitors. to ensure stable operation, there must be sufficient resistance in series with the inductor and output capacitor (see output capacitor stablility considerations ). output overshoot (v soar ) determines the minimum output capacitance requirement (see output capacitor selection). often the switching frequency is increased to 1000khz or 600khz, and the inductor value is reduced to minimize the energy transferred from induc- tor to capacitor during load-step recovery. the efficien- cy penalty for operating at 1000khz is about 5% and MAX1813 dh lx vpcs pgnd dl gnd ref fb v out c out q 2 c fb c vpcs r vpcs q 1 r fb r5 r6 r7 logic add0 add1 control logic inh r8 l1 r sense c ref v cc max4634 max4322 figure 18. adding a negative offset voltage
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning 36 ______________________________________________________________________________________ about 2-3% at 600khz when compared to the 300khz voltage-positioned circuit, primarily due to the high-side mosfet switching losses. pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 19). if possible, mount all of the power compo- nents on the top side of the board, with their ground terminals flush against one another. follow these guide- lines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) connect all analog grounds to a separate solid cop- per plane, which connects to the MAX1813 s gnd pin. this includes the v cc , ref, and cc capacitors, as well as the resistive-dividers connected to fb and ilim. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. 4) vpcs and gnd connections for current limiting and voltage positioning must be made using kelvin sensed connections to guarantee the current-sense accuracy. 5) when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it s better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 6) ensure the fb connection to the output is short and direct. 7) route high-speed switching nodes away from sensi- tive analog areas (cc, ref, ilim). make all pin-strap control input connections (skp/sdn, ilim, code, sus, zmode, etc.) to analog ground or v cc rather than power ground (pgnd) or v dd . d1 via to v+ via to lx via to fb via to source of q2 via to gnd near r sense via to vpcs inductor discharge path has low dc resistance. v dd all analog grounds connect to local plane only notes: ?tar?ground is used. d1 is directly across q2. connect local analog ground plane directly to gnd from the side opposite the v dd capacitor gnd to avoid v dd ground currents from flowing in the analog ground plane. MAX1813 battery input l1 v out q2 q1 r sense d1 gnd input gnd output pgnd gnd v cc cc ref c out c in figure 19. power-stage pc board layout example
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning ______________________________________________________________________________________ 37 v cc output 0.925v to 1.6v battery 2v to 28v +5v input MAX1813 ilim cc time ton lx v+ dh bst vpcs pgnd gnd zmode dl sus v cc ref s1 s0 d0 d2 d1 d3 d4 skip v dd fb pgood code dac inputs suspend mode typical operating circuit layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate trace must be short and wide (50mils to 100mils wide if the mosfet is 1 inch from the controller ic). 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 19. this diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; and an analog ground plane where sensitive analog components, the gnd pin, and v cc bypass capacitor go. the gnd plane and pgnd plane must meet only at a single point directly beneath the ic. these two planes are then connected to the high-power output ground with a short connection from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. chip information transistor count: 8757
MAX1813 dynamically-adjustable, synchronous step-down controller with integrated voltage positioning maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information qsop.eps

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